Efficient Memory Management for High-Speed ATM Systems

ATM technology places strict performance requirements on ATM systems, especially considering the scalability of the SDH/SONET physical layer to high speeds. Throughput preservation of the link speed through protocols to a higher layer application is a known problem in high-speed communication systems. The problem is being addressed with design methodologies that offer high speed data paths, using specialized hardware, and increased processing power, commonly in the form of embedded processors. In this paper, we present a case study for a high-speed Queue Manager for ATM systems. The manager enables high-speed data transfer to/from system memory and management of logical data structures (queues). Furthermore, it provides high-speed and importantly, scalability and re-usability, so that it can be used in a wide range of ATM systems, such as workstation adapters, switches, routers, etc. In this work, we provide contributions in two directions. We describe an approach to develop a high-speed, scalable and re-usable memory manager for ATM systems, and then we provide an architecture and implementations in harware as well as in software for embedded systems. The results indicate the cost/performance trade-off’s and system scalability and thus, enable designers to choose the implementation that meets their target system requirements well.